SPT674 f ast , complete 12-bit m p comp a tible a/d converter with sample/hold features ? improved high-performance version of the hadc574z ? complete 12-bit a/d converter with sample/hold, reference and clock ? low power dissipation (120 mw max) ? 12-bit linearity (over temp) ? 15 m s max conversion time ? single +5 v supply ? full bipolar and unipolar input range applications ? data acquisition systems ? 8 or 12-bit m p input functions ? process control systems ? test and scientific instruments ? personal computer interface general description the SPT674 is a complete, 12-bit successive approximation a/d converter manufactured in cmos technology. the de- vice is an improved version of the hadc574z. included on chip are an internal reference, clock, and a sample-and-hold. the s/h is an additional feature not available on similar devices. the SPT674 features 15 m s (max) conversion time of 10 or 20 v input signals. also, a three-state output buffer is added for direct interface to an 8, 12, or 16-bit m p bus. the SPT674 has standard bipolar and unipolar input ranges of 10 v and 20 v that are controlled by a bipolar offset pin and laser trimmed for specified linearity, gain and offset accuracy. the power supply is +5 v. the device also has an optional mode control voltage which may be used depending on the application. with a maximum dissipation of 120 mw at the specified voltages, power consumption is about five times lower than that of currently available devices. the SPT674 is available in a 28-lead ceramic sidebrazed dip package in the commercial temperature range. block diagram three-s tate buf fers and control nibble a nibble b nibble c 12-bit sar + - comp clock of fset/gain t rim control logic 12-bit capacitance dac sts a oc e agnd 20 v in 12/8 cs r/c ref ref out 10 v in bip of f output
SPT674 electrical specifications t a = t min to t max , v ee = 0 to +5 v, v dd = +5 v, f s = 117 khz, f in = 10 khz, unless otherwise specified.. test test SPT674c SPT674b parameter conditions level min typ max min typ max units dc electrical characteristics resolution vi 12 12 bits linea rity error t a = 0 to +70 cv i 1 0.5 lsb differential linearity no missing codes vi 12 12 bits unipolar offset; 10 v, 20 v +25 c adjustable to zero vi 4 4 lsb bipolar offset; 5 v, 10 v +25 c adjustable to zero vi 10 6 lsb full scale calibration error 1 +25 c adjustable to zero vi 0.30 0.30 % of fs full scale calibration error 1 no adjustment to zero t a = 0 to +70 c v 0.47 0.37 % of fs temperature coefficients using internal reference unipolar offset v 1.0 1.0 ppm/ c bipolar offset v 2.0 2.0 ppm/ c full scale calibration v 12 12 ppm/ c power supply rejection max change in full vi 0.5 0.5 lsb +4.75 v SPT674 electrical specifications t a = t min to t max , v ee = 0 to +5 v, v dd = +5 v, f s = 117 khz, f in = 10 khz, unless otherwise specified. test test SPT674c SPT674b parameter conditions level min typ max min typ max units dc electrical characteristics power supplies operating voltage range v dd iv +4.5 +5.5 +4.5 +5.5 volts v ee 2 iv v dd v dd volts operating current i dd iv 15 24 15 24 ma i ee 2v ee = +5 v i v 167 167 m a power dissipation vi 75 120 75 120 mw internal reference voltage vi 2.4 2.5 2.6 2.4 2.5 2.6 volts output current 3 vi 0.5 0.5 ma digital characteristics logic inputs (ce, cs , r/ c , ao, 12/ 8 ) logic 0 v i -0.5 +0.8 -0.5 +0.8 volts logic1 vi 2.0 5.5 2.0 5.5 volts current vi -5.0 0. 1 5.0 -5.0 0. 1 5.0 m a capacitance v 5 5 p f logic outputs (db11-db0, sts) logic 0 ( i sink = 1.6 ma) vi +0.4 +0.4 volts logic 1 ( i source = 500 m a) vi +2.4 +2.4 volts leakage (high z state, vi -5 0.1 +5 -5 0.1 +5 m a db11-db0 only) capacitance v 5 5 p f ac accuracy f s =117 khz, f in =10 khz spurious free dyn. range v 7 3 7 8 7 6 7 8 d b total harmonic distortion v -77 -72 -77 -75 db signal-to-noise ratio v 6 9 7 2 7 1 7 2 d b signal-to-noise & distortion v 6 8 7 1 7 0 7 1 d b (sinad) intermodulation distortion f in =20 khz; v -75 -75 db f in2 =23 khz note 1: fixed 50 w resistor from ref out to ref in and ref out to bip off. note 2: v ee is optional and is only used to set the mode for the internal sample/hold. when not using v ee , the pin should be treated as a no connect. if v ee is connected to 0 to -15 v, aperture delay (t ap ) will increase from 20 ns (typ) to 4000 ns (typ). note 3: available for external loads; external load should not change during conversion. 3 8/1/00
SPT674 electrical specifications t a = t min to t max , v ee = 0 to +5 v, v dd = +5 v, f s = 117 khz, f in = 10 khz, unless otherwise specified. test test SPT674c SPT674b parameter conditions level min typ max min typ max units ac electrical characteristics 4 convert mode timing t dsc sts delay from ce vi 60 200 60 200 ns t hec ce pulse width vi 50 30 50 30 ns t ssc cs to ce setup vi 50 20 50 20 ns t hsc cs low during ce high v i 5 0 2 0 5 0 2 0 n s t src r/ c to ce setup vi 50 0 5 0 0 ns t hrc r/ c low during ce high v i 5 0 2 0 5 0 2 0 n s t sac ao to ce setup vi 0 0 ns t hac ao valid during ce high v i 5 0 2 0 5 0 2 0 n s t c conversion time 5 12-bit cycle vi 9 1 3 1 5 9 13 15 m s 8-bit cycle vi 6 8 10 6 8 10 m s read mode timing t dd access time from ce vi 75 150 75 150 ns t hd data valid after ce low vi 25 35 25 35 ns t hl output float delay vi 100 150 100 150 ns t ssr cs to ce setup vi 50 0 5 0 0 ns t srr r/ c to ce setup vi 0 0 ns t sar ao to ce setup vi 50 25 50 25 ns t hsr cs valid after ce low vi 0 0 ns t hrr r/ c high after ce low vi 0 0 ns t hs sts delay after data valid v i 1 0 0 3 0 0 6 0 0 1 0 0 3 0 0 6 0 0 n s t har ao valid after ce low vi 50 50 ns note 4: time is measured from 50% level of digital transitions. note 5: includes acquisition time. t hec t ssc t src t hsc t hrc t hac t sac t dsc high impedance t c db1 1-db0 sts ao r/c ce cs figure 1 - convert mode timing diagram figure 2 - read mode timing diagram t ssr ao ce cs t hsr t hrr t srr t sar t har sts d ata v alid t hl high impedance db1 1-db0 r/c t hs t hd t dd 4 8/1/00
SPT674 electrical specifications t a = t min to t max , v ee = 0 to +5 v, v dd = +5 v, f s = 117 khz, f in = 10 khz, unless otherwise specified. test test SPT674c SPT674b parameter conditions level min typ max min typ max units ac electrical characteristics 4 stand-alone mode timing t hrl low r/ c pulse width vi 25 25 ns t ds sts delay from r/ c vi 200 200 ns t hdr data valid after r/ c low vi 25 25 ns t hs sts delay after data valid vi 100 300 600 100 300 600 ns t hrh high r/ c pulse width vi 100 100 ns t ddr data access time vi 150 150 ns sample-and-hold aperture delay v ee = +5 v i v 2 0 2 0 n s aperture uncertainty time v ee = +5 v v 300 300 ps, rms figure 4 - high pulse for r/ c - outputs enabled while r/ c is high, otherwise high impedance figure 3 - low pulse for r/ c - outputs enabled after conversion r/c t hrl da t a v alid da t a v alid db1 1-db0 sts t ds t c t hdr t hs db1 1-db0 t hrh sts t c t ddr t ds t hdr da t a v alid high-z r/c high-z test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi 5 8/1/00
SPT674 circuit operation the SPT674 is a complete 12-bit analog-to-digital converter that consists of a single chip version of the industry standard 674. this single chip contains a precision 12-bit capacitor digital-to-analog converter (cdac) with voltage reference, comparator, successive approximation register (sar), sample- and-hold, clock, output buffers and control circuitry to make it possible to use the SPT674 with few external components. when the control section of the SPT674 initiates a conversion command, the clock is enabled and the successive-approxi- mation register is reset to all zeros. once the conversion cycle begins, it cannot be stopped or restarted and data is not available from the output buffers. the sar, timed by the clock, sequences through the conver- sion cycle and returns an end-of-convert flag to the control section of the adc. the clock is then disabled by the control section, the output status goes low, and the control section is enabled to allow the data to be read by external command. the internal SPT674 12-bit cdac is sequenced by the sar starting from the msb to the lsb at the beginning of the conversion cycle to provide an output voltage from the cdac that is equal to the input signal voltage (which is divided by the input voltage divider network). the comparator determines whether the addition of each successively-weighted bit volt- age causes the cdac output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. after testing all the bits, the sar contains a 12-bit binary code which accurately represents the input signal to within 1/2 lsb. the internal reference provides the voltage reference to the cdac with excellent stability over temperature and time. the reference is trimmed to 2.5 volts and can supply at least 0.5 ma to an external load. any external load on the SPT674 reference must remain constant during conversion. the sample-and-hold feature is a bonus of the cdac archi- tecture. therefore the majority of the s/h specifications are included within the a/d specifications. although the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of the capacitive dac makes the SPT674 appear to have a built-in sample- and-hold. this sample-and-hold action substantially in- creases the signal bandwidth of the SPT674 over that of similar competing devices. note that even though the user may use an external sample- and-hold for very high frequency inputs, the internal sample- and-hold still provides a very useful isolation function. once the internal sample is taken by the cdac capacitance, the input of the SPT674 is disconnected from the users sample- and-hold. this prevents transients occurring during conver- sion from affecting the attached sample-and-hold buffer. all other 674 circuits will cause a transient load current on the sample-and-hold which will upset the buffer output and may add error to the conversion itself. furthermore, the isolation of the input after the acquisition time in the SPT674 allows the user an opportunity to release the hold on an external sample-and-hold and start it tracking the next sample. this increases system throughput with the users existing components. typical interface circuit the SPT674 is a complete a/d converter that is fully opera- tional when powered up and issued a start convert signal. only a few external components are necessary as shown in figures 5 and 6. the two typical interface circuits are for operating the SPT674 in either an unipolar or bipolar input mode. information on these connections and on conditions concerning board layout to achieve the best operation are discussed below. for each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digital sections), and grounding. digital timing, calibration and the analog signal source must be considered for correct operation. power supplies the supply voltage for the SPT674 must be kept as quiet as possible from noise pickup and also regulated from transients or drops. because the part has 12-bit accuracy, voltage spikes on the supply lines can cause several lsb deviations on the output. switching power supply noise can be a problem. careful filtering and shielding should be employed to prevent the noise from being picked up by the converter. v dd should be bypassed with a 10 m f tantalum capacitor located close to the converter to filter noise and counter the problems caused by the variations in supply current. v ee is only used as a logic input and is immune to typical supply variation. grounding considerations resistance of any path between the analog and digital grounds should be as low as possible to accommodate the ground currents present with this device. to achieve specified accuracy, a double-sided printed circuit board with a copper ground plane on the component side is recommended. keep analog signal traces away from digital lines. it is best to lay the pc board out such that there is an analog section and a digital section with a single point ground connection between the two through an rf bead located as close to the device as possible. if possible, run analog signals between ground traces and cross digital lines at right angles only. 6 8/1/00
SPT674 the gain adjustment should be done at positive full scale. the ideal input corresponding to the last code change is applied. this is 1 and 1/2 lsb below the nominal full scale which is +9.9963 v for the 10 v range and +19.9927 v for the 20 v range. adjust the gain potentiometer r2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. if calibration is not necessary for the intended application, replace r2 with a 50 w , 1% metal film resistor and remove the network from t h e bip off pin . connect the bip off pin to agnd. connect the analog input to the 10 v in pin for the 0 to 10 v range or to the 20 v in pin for the 0 to 20 v range. bipolar the gain and offset errors listed in the specification may be adjusted to zero using the potentiometers r1 and r2. (see figure 6.) if adjustment is not needed, either or both pots may be replaced by a 50 w , 1% metal film resistor. to calibrate, connect the analog input signal to the 10 v in pin for a 5 v range or to the 20 v in pin for a 10 v range. first apply a dc input voltage 1/2 lsb above negative full scale which is -4.9988 v for the 5 v range or -9.9976 v for the 10 v range. adjust the offset potentiometer r1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. next, apply a dc input voltage 1 and 1/2 lsb below positive full scale which is +4.9963 v for the 5 v range or +9.9927 v for the 10 v range. adjust the gain potentiometer r2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. the analog and digital common pins should be tied together as close to the package as possible to guarantee best perfor- mance. the code dependent currents flow through the v dd terminal and not through the analog and digital common pins. range considerations the SPT674 may be operated by a microprocessor or in the stand-alone mode. the part has four standard input ranges: 0 v to +10 v, 0 v to +20 v, 5 v and 10 v. the maximum errors that are listed in the specifications for gain and offset may be adjusted externally to zero as explained in the next two sections. calibration & connection procedures unipolar the calibration procedure consists of adjusting the converters most negative output to its ideal value for offset adjustment and then adjusting the most positive output to its ideal value for gain adjustment. starting with offset adjustment and referring to figure 5, the midpoint of the first lsb increment should be positioned at the origin to get an output code of all 0s. to do this, an input of +1/2 lsb or +1.22 mv for the 10 v range and +2.44 mv for the 20 v range should be applied to the SPT674. adjust the offset potentiometer r1 for code transition flickers between 0000 0000 0000 and 0000 0000 0001. figure 5 - unipolar input connections v ref in control logic nib b le a nib b le b nib b le c three-state buff ers and control oscillator 12-bit sar 12-bits 12-bits ref offset/gain t r im netw or k ref amp sample/hold output bits v ref out bip off 20 v in 10 v in sts v dd dgnd msb lsb strobe analog inputs (calibr ation) .1 f +5 v r2 100 w 0 to 10 v 0 to 20 v ao ce cs r/c 12/8 100 k w 100 k w -15 v +15 v r1 100 w cd a c comp v ee control logic nib b le a nib b le b nib b le c three-state buff ers and control oscillator 12-bit sar 12-bits 12-bits ref offset/gain t r im netw or k ref amp sample/hold output bits v ref out bip off 20 v in 10 v in sts v dd dgnd msb lsb strobe v ref in analog inputs .1 f +5 v ? v 10 v ao ce cs r/c 12/8 cd a c comp 100 w r1 100 w r1 v ee figure 6 - bipolar input connections 7 8/1/00
SPT674 alternative in some applications, a full scale of 10.24 v (for an lsb of 2.5 mv) or 20.48 v (for an lsb of 5.0 mv) is more convenient. in the unipolar mode of operation, replace r2 with a 200 w potentiometer and add 150 w in series with the 10 v in pin for 10.24 v input range or 500 w in series with the 20 v in pin for 20.48 v input range. in bipolar mode of operation, replace r1 with a 500 w potentiometer (in addition to the previous changes). the calibration will remain similar to the standard calibration procedure. controlling the SPT674 the SPT674 can be operated by most microprocessor sys- tems due to the control input pins and on-chip logic. it may also be operated in the stand-alone mode and enabled by the r/ c input pin. full m p control consists of selecting an 8 or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready. the output read has the options of choosing either 12-bits at once or 8 bits followed by 4-bits in a left-justified format. all five control inputs are ttl/ cmos compatible and include 12/ 8 , cs , ao, r/ c and ce. the use of these inputs in controlling the converters opera- tions is shown in table i, and the internal control logic is shown in a simplified schematic in figure 10. stand-alone operation the simplest interface is a control line connected to r/ c . the output controls must be tied to known states as follows: ce and 12/ 8 are wired high, ao and cs are wired low. the output data arrives in words of 12-bits each. the limits on r/ c duty cycle are shown in figures 3 and 4. it may have a duty cycle within and including the extremes shown in the specifica- tions. in general, data may be read when r/ c is high unless sts is also high, indicating a conversion is in progress. table i - truth table for the SPT674 control inputs ce ao operation cs r/c 12/8 0 xxxx none x 1 x x x none 0 0 x 0 initiate 12 bit conversion 0 0 x 1 initiate 8 bit conversion 1 0 x 0 initiate 12 bit conversion 1 0 x 1 initiate 8 bit conversion 1 0 x 0 initiate 12 bit conversion 1 0 x 1 initiate 8 bit conversion 10 1x 1 enable 12 bit output 10 00 1 enable 8 msb's only 10 01 1 enable 4 lsb's plus 4 trailing zeroes figure 7 - interfacing the SPT674 to an 8-bit data bus address bus ao ~ data bus sts msb dig com lsb ao 12/8 controlled operation conversion length a conversion start transition latches the state of ao as shown in figure 7 and table i. the latched state determines if the conversion stops with 8 bits (ao high) or continues for 12 bits (ao low). if all 12 bits are read following an 8-bit conversion, the three lsbs will be a logic 0 and db3 will be a logic 1. ao is latched because it is also involved in enabling the output buffers as will be explained later. no other control inputs are latched. conversion start a conversion may be initiated by a logic transition on any of the three inputs: ce, cs , r/ c , as shown in table i. the last of the three to reach the correct state starts the conversions, so one, two or all three may be dynamically controlled. the nominal delay from each is the same and all three may change state simultaneously. in order to assure that a par- ticular input controls the start of conversion, the other two should be set up at least 50 ns earlier. refer to the convert mode timing specifications. the convert start timing diagram is illustrated in figure 1. the output signal sts is the status flag and goes high only when a conversion is in progress. while sts is high, the output buffers remain in a high impedance state so that data can not be read. also, when sts is high, an additional start convert will not reset the converter or reinitiate a conversion. note, if ao changes state after a conversion begins, an additional start convert command will latch the new start of ao and possibly cause a wrong cycle length for that conver- sion (8 versus 12 bits). 8 8/1/00
SPT674 reading the output data the output data buffers remain in a high impedance state until the following four conditions are met: r/ c is high, sts is low, ce is high, and cs is low. the data lines become active in response to the four conditions and output data according to the conditions of 12/ 8 and ao. the timing diagram for this process is shown in figure 2. when 12/ 8 is high, all 12 data outputs become active simultaneously and the ao input is ignored. this is for easy interface to a 12 or 16-bit data bus. the 12/ 8 input is usually tied high or low, although it is ttl/cmos compatible. when 12/ 8 is low, the output is separated into two 8-bit bytes as shown below. figure 8 - output when 12/ 8 is low x x x x x x x x byte 1 msb o o o o x x x x byte 2 lsb this configuration makes it easy to connect to an 8-bit data bus as shown in figure 7. the ao control can be connected to the least significant bit of the address bus in order to store the output data into two consecutive memory locations. when ao is pulled low, the 8 msbs are enabled only. when ao is high, the 4 msbs are disabled, bits 4 through 7 are forced to a zero and the four lsbs are enabled. the two byte format is left justified data as shown above and can be considered to have a decimal point or binary to the left of byte 1. ao may be toggled without damage to the converter at any time. break-before-make action is guaranteed between the two data bytes. this assures that the outputs in figure 7 will never be enabled at the same time. in figure 2, it can be seen that a read operation usually begins after the conversion is completed and sts is low. if earlier access is needed, the read can begin no later than the addition of time t dd and t hs before sts goes low. sample-and-hold (s/h) control mode this control mode is provided to allow full use of the internal s/h, eliminating the need for an external s/h in most applica- tions. the SPT674 in the control mode also eliminates the need for one of the control signals, usually the convert command. the command that puts the internal s/h in the hold state also initiates a conversion, reducing time con- straints in many systems. as soon as the conversion is completed the internal s/h immediately begins slewing to track the input signal. see figure 9. in the control mode it is assumed that during the required 1.4 m s acquisition time the signal is not slewing faster than the slew rate of the SPT674. no assumption is made about the input level after the convert command arrives since the input signal is sampled and conversion begins immediately after the convert command. this means that the convert com- mand can be used to switch an input multiplexer or change gains on a programmable gain amplifier, allowing the input signal to settle before the next acquisition at the end of the conversion. because aperture jitter is minimized by the internal s/h, a high input frequency can be converted without an external s/h. see table ii. table ii - conversion timing (v ee = +5 v) s/h control mode parameter min typ max units throughput time (t aq + tc ) 12-bit conversions 13 15 m s 8-bit conversions 8 1 0 m s conversion time (t c ) 12-bit conversions 11.4 m s 8-bit conversions 6.4 m s acquisition time(t ac ) 1.4 m s aperture delay (t ap )2 0 n s aperture uncertainty (t j ) 0.3 ns figure 9 - s/h control mode timing (v ee = +5 v) t ap t c r/c t aq signal acquisition conversion signal acquisition 9 8/1/00
SPT674 figure 10 - control logic input buf fers read control eoc8 eoc12 nibble b zero override nibble a,b nibble c ck q d q a o latch ce r/c a cs 12/8 d q ck r delay sts h 10 8/1/00
SPT674 a b c d e f g 1 28 i h j inches millimeters symbol m i n m a x m i n m a x a 0.077 0.093 1.96 2.36 b 0.016 0.020 0.41 0.51 c 0.095 0.105 2.41 2.67 d .050 typ 1.27 typ e 0.040 0.060 1.02 1.52 f 0.215 0.235 5.46 5.97 g 1.388 1.412 35.26 35.86 h 0.585 0.605 14.86 15.37 i 0.009 0.012 0.23 0.30 j 0.600 0.620 15.24 15.75 28-lead sidebrazed package outline 11 8/1/00
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